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DOC Title EK7601 Data Sheet
DOC NO REV Page / Revision History / / Revise item / Content .0 /
TDS760 -0
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REV Date 2002/02/2
Eff. Date 2002/3/5
REV. Page
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Eureka
Microelectronics, Inc.
EK7601
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.com
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240-Channel Analogue Source Driver for colour TFT LCDs
6F, NO.12, INNOVATION 1 . RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. TEL 886-3-5799255 FAX 886-3-5799253 http://www.eureka.com.tw
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for colour TFT LCDs
OVERVIEW
EK7601
240-Channel Analogue Source Driver
The EM7601 is an analogue, fully colour, source driver for TFT LCD panels designed for camera, TV etc. Analogue R, G and B signal are applied directly on the chip. For each of the 240 outputs, the voltage is sampled and buffered to the panel. With a double sample and hold circuit a new voltage can be sample whereas the previous sample voltage is applied to the panel. According to different modes, the 3 input voltages (VA, VB, VC) can be applied on different output to support various pixel array types. The 3 input voltages (VA, VB, VC) can be sampled simultaneously or sequentially to have a better flexibility with the input voltage. Using enable signal (STHx), several chips can be cascaded for large panel.
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FEATURE
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*
* * * * * * * * * * *
LCD outputs: 240 Bi-directional shift (L/R) Simultaneous or Sequential RGB acquisition mode X1 or X3 clock mode High frequency Sampling 10MHz (x1) Automatic low power consumption mode after data capture (gated clock) RGB colour selection (automatic or manual) Applicable to COG / COF Logic power supply voltage VDD: 2.7V - 5.25V LCD power supply voltage AVDD: 4.5V - 5.5V Output dynamic range AVSS+0.2V to AVDD-0.2V Applicable to COG/COF
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1. INTERNAL BLOCK DIAGRAM
QA1
INH
EK7601
QC1 QA2 QA80 QB80 QC80
QB1
+
+
+
+
+
+
+
-
-
-
-
-
-
Line Control
AMUX
AMUX
AMUX
AMUX
AMUX
AMUX
MUX
Q1H Q2H VA (R) VB (G) VC (B) TEST2
AMUX
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
MUX
MUX
MUX
MUX
L/R STH1 CPH1 Clock MUX SR SR SR SR SR SR SR STH2
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MUX
CPH3 MODE
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MUX
AMUX
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Figure 1.1:
Block diagram
1. Clock MUX Selects if the sampling is simultaneous or sequential and the clocks are divided by three or not. Also gates the clock. 2. 3 x 80-bit bi-directional shift register Generates enable signals for sequential sampling 80 groups of 3 input colours. 3. Line control Select sample circuit SHA or SHB and the high impedance output state 4. SH control MUX Select which sample and hold circuit samples the analogue input value. 5. RGB MUX According to the controls signals, selects which input colour goes to which group of outputs. 6. Sample and hold Circuit (SHA, SHB) Sample the input voltage when the enable signal of the shift register is generated and hold this value until it is stored on the panel. 7. Buffers Drive the sample greyscale voltage on the panel.
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2. PIN CONFIGURATION (COF PACKAGE)
EK7601
COM COM COM COM COM RESET MODE INH STH1 CPH3 CPH2 CPH1 VDD AVDD
COM COM COM COM COM Qa1 Qb1 Qc1
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NC TEST2 AVSS VC VB VA VSS STH2 Q2H Q1H L/R COM COM COM COM COM
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Qa80 Qb80 Qc80 COM COM COM COM COM
Figure 2.1:
Pin Arrangement
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3. PIN FUNCTION DESCRIPTION Signal Name Qa1 to Qa80 Qb1 to Qb80 Qc1 to Qc80 VA VB VC L/R STH1 Pin Type Output
EK7601
Function Liquid-crystal application voltages Each QaX, QbX or QcX correspond to one of the analogue sample input signal VA, VB or VC. Video input signal Analogue video input signal that is sampled internally and applied to the panel. Controls the display data shift direction L/R = H : STH1 input, Qa1Qc80, STH2 output. L/R = L : STH2 input, Qc80Qa1, STH1 output. Right shift start pulse L/R = H : Becomes the start pulse input pin L/R = L : Becomes the start pulse output pin Left shift start pulse L/R = H : Becomes the start pulse output pin L/R = L : Becomes the start pulse input pin Sampling clock input Refers to the analogue data-sampling clock. The sampling starts at the first rising edge of CPH1 when STH1 (L/R=H) is activated. CPH1 can be internally divided (x3 mode) to generate internal clock signal CPH1'. The sampling can be simultaneous or sequential. .com In simultaneous mode, the sampling is made during CPH1 (CPH1') period for all output. In sequential mode, the sampling is made according the table below: CPH1 (CPH1') control the sampling for Qa1Qa80 CPH2 (CPH2') control the sampling for Qb1Qb80 CPH3 (CPH3)' control the sampling for Qc1Qc80 When clock mode x1 and sequential is selected, the three inputs CPH1, CPH2 and CPH3 must have an input clock signal applied. Otherwise only CPH1 must have input clock applied. The clock selection table was described on the page 8. Load line The sampled voltages are connecting to the panel at the rising edge of INH. The outputs of SHA(B) that was in sample mode are applied to the panel, whereas the SHB(A) becomes ready to sample new values. During INH = L, output level is HiZ state and this signal initialise the internal circuits.
Input
Input
Bidir
STH2
Bidir
CPH1 CPH2 CPH3
Input (Pull-down CPH2 & CPH3 @ TEST2 = L And MODE=H)
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INH
Input
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TEST2 Input (Pull-up)
EK7601
MODE
Input (Pull-down @ TEST2 = L) Input (Pull-down @ TEST2 = L)
Q1H Q2H
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RESET
Input (Pull-down @ TEST2 = L)
VDD VSS AVDD AVSS
Power Power Power Power
Input signal colour rotation mode selector TEST2 = L: No data rotation mode. Input voltage of each output QaX, QbX and QcX are selected from VA, VB and VC according to the control signal Q1H and Q2H. Simultaneous or sequential clock mode is selected by MODE. TEST2= H or open: Automatic rotation mode. Input voltage of each output QaX, QbX and QcX are selected automatically from VA, VB and VC according to the filter arrays, selected by the control signal Q1H and Q2H. Simultaneous or sequential clock mode is selected by Q1H, Q2H. Sampling mode selection MODE = L or open: Sequentially sampling MODE = H: Simultaneous sampling This signal is only usable when TEST2= L. Colour selection input When TEST2 = L: Q1H and Q2H select which input voltage (VA, VB, VC) correspond to QaX, QbX, QcX outputs. When TEST2 =H: Q1H and Q2H select the filters array colours sequence. Q1H and Q2H select also simultaneous/sequential mode according to the equation below. Q1H = Q2H = 0: Simultaneous sampling Q1H =1 OR Q2H = 1: Sequential sampling The colour selection table and filter array are describe on page 12. .com Automatic colour selection Initialisation Reset the system of the automatic rotation mode. To initialise the module a pulse on INH must be applied after reset. This function is only usable when TEST2=H. When not used should be L or open. Logic part power supply Logic part ground Analogue part power supply Analogue part ground
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4. OPERATION TIMING
Line CPH1
1 2 3 4 78 79 80 81 82 319 320 321
EK7601
1
2
STH1 VA VB VC
A1 A2 A3 A78 A79 A80 A81 A319 A320 A1
B1
B2
B3
B78
B79
B80
B81
B319
B320
B1
C1
C2
C3
C78
C79
C80
C81
C319
C320
C1
INH STH2
1 Chip
st
STH2
Last Chip
Sample circuits Buffers Ouputs Drivers Outputs High Z L/R = H shift from left to right Clock mode : x1 simultaneous
SHA Line n Line n-1 Line n-1 No rotation mode Ax, Bx, Cx correspond to the sample values for the VA -> QAx outputs QAx, VB -> QBx .com QBx, QCx. VC -> QCx
SHB Line n+1 Line n High Z Line n
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Figure 4.1:
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Operation timing diagram
The start condition is initiated by applying a start pulse to the enable input pin (STH1 when L/R=VDD) at the beginning of each line on the first chip. During the next 80 CPH1 rising edges, this source driver sample 80 times 3 display input voltage (3 RGB dot x 80 pixels). After sampling th the 80 group of input voltages, it activates the enable output signal (STH2 when L/R=VDD) to enable the following chip. As soon as the loading of the input voltage is achieved for a complete line, the controller activates the INH signal to force the 240 output buffers in a high impedance state. Then the outputs of SHA(B) that were in sample mode are applied to the output buffers , whereas the SHB(A) becomes ready to sample new values. Finally, at the rising edge of INH, the 240 output buffers drive the sample voltages to the panel.
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5. SAMPLING MODES When TEST2 =L Mode=H Mode=L When TEST2 =H Q1H=Q2H=L Q1H=H OR Q2H =H Sampling Mode Simultaneous Sequential
EK7601
Simultaneous/Sequential and x1/x3 sampling modes provide 4 different ways to sample input voltages. Simultaneous/Sequential selection mode is described on the table below.
Table 5.1:
Simultaneous Sequential selection table
Sampling Mode Simultaneous Sequential Simultaneous Sequential Table 5.2:
CPH1 Clock IN Clock IN Clock IN Clock IN
CPH2 L Clock IN L L
CPH3 L Clock IN H H
Clock division x1 x3
x1 x3 clock selection table
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All diagram below describe the 4 clock modes, voltage correspondence are: VA -> QAX, VB -> .com QBX, VC -> QCX. Ax, Bx, Cx correspond to the sample values for the outputs QAx, QBx, QCx.
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CPH1 CPH2 CPH3 STH1 VA VB VC STH2
1
2
3
4
78
79
80
81
A1
A2
A3
A78
A79
A80
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
L/R = H shift from left to right CPH2 = CPH3 = L
MODE = H when TEST2 = L OR Q1H = Q2H = L when TEST2 = H
Figure 5.1:
x1 simultaneous sampling mode
Each input is sampled simultaneously synchronised with CPH1 rising edge. th Output enable signal is generated at the falling edge of the 80 period of CPH1 since the start pulse. -8Rev 1.0 Feb.21.2002
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CPH1 CPH2 CPH3 STH1 VA VB VC STH2 L/R = H shift from left to right CPH2, CPH3 : clock input MODE = L when TEST2 = L OR Q1H = H or Q2H = H when TEST2 = H
A1 A2 A3 A78 A79 1 2 3 4 78 79 80 1 2 3 4 78 79
EK7601
81
80
81
1
2
3
4
78
79
80
81
A80
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
Figure 5.2:
x1 sequential sampling mode
t4U.com
Each input is sampled sequentially synchronised with the associated rising edge of the corresponding clock. CPH1 controls the sample for QAx outputs, CPH2 controls the sample for QBx outputs and CPH3 controls the sample for QCx outputs. .com th Output enable signal is generated at the falling edge of the 80 period of CPH1 since the start pulse.
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CPH1
1 2 3 4 5 6 7 8 9 10 11
EK7601
234 235 236 237 238 239 240 241 242 243 244 245
CPH2 CPH3 STH1 CPH1' VA VB VC STH2 L/R = H shift from left to right CPH2 = L CPH3 = H MODE = H when TEST2 = L OR Q1H = Q2H = L when TEST2 = H
1 A1 2 A2 3 A3 4 78 A78 79 A79 80 A80 81
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
Figure 5.3:
x3 simultaneous sampling mode
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.com Each input is sampled simultaneously synchronised with CPH1' rising edge. CPH1' is generated from CPH1 (Frequency divided by 3). th Output enable signal is generated at the falling edge of the 80 period of CPH1' since the start pulse.
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CPH1
1 2 3 4 5 6 7 8 9 10 11
EK7601
234 235 236 237 238 239 240 241 242 243 244 245
CPH2 CPH3 STH1 CPH1' CPH2' CPH3' VA VB VC STH2
A1 1 2 3 4 78 79 80 81
1
2
3
4
78
79
80
81
1
2
3
4
78
79
80
81
A2
A3
A78
A79
A80
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
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L/R = H shift from left to right CPH2 = L CPH3 = H
.com H when TEST2 = H Q1H = H or Q2H =
MODE = L when TEST2 = L OR
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Figure 5.4:
x3 sequential sampling mode
Each input is sampled sequentially synchronised with the associated rising edge of the corresponding clock. CPH1' controls the sample for QAx outputs, CPH2' controls the sample for QBx outputs and CPH3' controls the sample for QCx outputs. CPH1', CPH2' and CPH3' are generated from CPH1 (Frequency divided by 3). The three clocks have one CPH1 period phase shift between them. th Output enable signal is generated at the falling edge of the 80 period of CPH1' since the start pulse.
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6. COLOUR MODE SELECTION NO ROTATION MODE
EK7601
According to the signal description table, the colour mode selection is separated in two modes. No rotation mode and automatics rotation mode.
This mode is selected by TEST2 = L. When no rotation mode is selected, Q1H and Q2H control the colour selection in order to the table below. Q1H L L H Table 6.1: Q2H L H X QA VA VC VB QB VB VA VC QC VC VB VA
No rotation mode colour selection table
The sample circuit SHA(B) get the value according to the table above. For example, when Q1H = Q2H = L, the sample circuit SHA(B) for the outputs Qax sample VA and the next INH pulse this sample voltage is put to the panel. AUTOMATIC ROTATION MODE This mode is selected by TEST2 = H. It allows the chip to select automatically the colour in function of the panel colour filter and the chips location on the panel (single bank or dual bank). Single bank mean that all the source drivers are on one side of the panel. Dual bank means that .com one group of source drivers is in the top of the panel and one at the bottom of the panel and they drive columns alternatively. Q1H L L H Table 6.2: Q2H L H X Colour array Vertical Stripe Delta Delta Chip location Single bank Single bank Dual bank
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Automatic rotation mode panel selection table
In this mode, the colour selection has a cycle of two lines. A pulse on RESET and after an activation of INH initialises this sequence (figure below).
RESET INH Sample QA1 to QC80 1st line sampling 2nd line sampling 1st line (Odd) 2nd line (Even)
Figure 6.1:
Automatic rotation mode initialisation sequence
In automatic rotation mode, the colour is selected automatically for Odd and Even line.
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Vertical stripe array This mode is selected by Q1H = Q2H = L and TEST2=H. The characteristics of this panel configuration are: * * Each column is associated with one colour. One bank of source driver.
Q1H = L Q2H = L VA = R VB = B VC = G
EK7601
EK7601
QC79 QA80 QB80 QC80 G G G G R R R R B B B B G G G G
QA1 QB1 QC1 QA2 QB2 QC2 1st line R(VA) B(VB) G(VC) nd 2 line R(VA) B(VB) G(VC) rd 3 line R B G 4th line R B G R R R R B B B B G G G G
Figure 6.2:
Vertical stripe array panel configuration
The figure shows, for this mode, that there is only one case of colour:
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Line Odd Even Table 6.3:
.com QA QB VA VB VA VB
QC VC VC
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Vertical stripe array colour selection table
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Single bank delta array This mode is selected by Q1H = L, Q2H = H and TEST2 = H. The characteristics of this panel configuration are: * * Each column is share between two colours. One bank of source driver.
Q1H = L Q2H = H VA = R VB = B VC = G
EK7601
EK7601
QC79 QA80 QB80 QC80 G R G R B B R G R G B R B R G G
QA1 QB1 QC1 QA2 QB2 QC2 1 line R(VA) B(VB) G(VC) R B G 2nd line B(VB) G(VC) R(VA) B G R 3rd line R B G R B G th 4 line B G R B G R
st
Figure 6.3:
Single bank delta array panel configuration
The colours are switched between Odd and Even line:
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Line Odd Even Table 6.4:
.com QA QB VA VB VB VC
QC VC VA
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Single bank delta array colour selection table
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Dual bank delta array This mode is selected by Q1H = H, Q2H = H and TEST2 = H. The characteristics of this panel configuration are: * * Each column is share between two colours. Two bank of source driver (top and bottom of the panel).
Q1H = H Q2H = H L/R = H VA = B VB = R VC = G QA1 1st line 2nd line 3rd line 4th line QB1 QC1
EK7601
EK7601
QA80 R B R B G G B R B R G B QB80 G B R G R G B R QC80 B R G G
R(VB) B(VC) G(VC) R(VB) B(VA) G(VA) B(VA) G(VA) R(VB) B(VC) G(VC) R(VB) B B G G R R B G R B G R
last-3 line last-2 line last-1 line last line
R B R B G G
B R B R
G B G B
R G R G
B R B R
G G
B B G G R R B G R B G R R(VB) B(VC) G(VC) R(VB) B(VA) G(VA) B(VA) G(VA) R(VB) B(VC) G(VC) R(VB) QC1 QB1 QA1
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QC80
QB80
.com QA80
DataShee
EK7601
Q1H = H Q2H = H L/R = L VA = G VB = R VC = B
Figure 6.4:
Dual bank delta array panel configuration
The colours are switched between Odd and Even line and depend also on L/R: L/R H L Line Odd Even Odd Even QA VB VA VA VB QB VC VB VB VC QC VA VC VC VA
Table 6.5:
Dual bank delta array colour selection table
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COLOURS SELECTION RESUMING TABLE The table below resume 3 different colour cases: Case 1 2 3 Table 6.6: QA VA VC VB QB VB VA VC QC VC VB VA
EK7601
RGB Colour selection case
The table below resume all colour selection modes: Q1H L L H H Table 6.7: Q2H L H H H LR X X L H When TEST2 =L 1 2 3 3 When TEST2 =H Odd line Even line 1 1 1 3 1 3 3 1
Colours selection resuming table
The numbers represent the different colour cases are listed on Table 6.6.
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7.
.com RELATIONSHIP BETWEEN INH AND OUTPUT WAVEFORM
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At INH rising edge, the sample voltages are output on the panel. As long as INH is active, the 240 output buffers are forced in a high impedance state.
INH
QA1 to QC80
Hi-Z Hi-Z Hi-Z Hi-Z
Figure 7.1:
INH timing diagram
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8. ELECTRICAL SPECIFICATION Absolute Maximum Rating (VSS = AVSS = 0 V) Parameter
Logic Part Supply Voltage Analogue Part Supply Voltage Logic Part Input Voltage Video Input Voltage Logic Part Output Voltage Driver Part Output Voltage Storage Temperature
EK7601
Symbol
VDD AVDD VI1 VI2 VO1 VO2 TSTG
Rating
-0.5 to +7.0V -0.5 to +7.0V -0.5 to VDD + 0.5 IVE ECT to AVDD + 0.5 OBJ -0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -55 to +125
Unit
V V V V V V C
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Caution: If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum rating, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum rating. .com
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Recommended Operating Range (VSS = AVSS = 0 V)
Parameter
Logic Part Supply Voltage Analogue Part Supply Voltage Video Input Voltage Operating Ambient Temperature Maximum Clock Frequency
Symbol
VDD AVDD VVIDEO TA
Conditions
MIN
2.7 4.5 AVSS + 0.2 -30
TYP
MAX
5.25 5.5 AVDD - 0.2 75 10 25 200
Unit
V V V C MHz MHz s
X1 Mode FCPH X3 Mode INH period TINH
IVE ECT OBJ
64
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DC Characteristics (TA= -30 to +75C, VDD= 2.7V to 5.25V, AVDD= 4.5V to 5.5V, VSS=AVSS=0V) Parameter
Logic High-level Input Voltage Logic Low-level Input Voltage Logic Input Leakage Current Video Input Leakage Current Logic High-level Output Voltage Logic Low-level Output Voltage Output Voltage Range Output Voltage Deviation Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption
EK7601
Symbol
VDIH VDIL ILIL IVIL VOH VOL V0 V0 IDD IADD CL1
Condition
MIN.
0.7*VDD 0.0
TYP.
MAX.
VDD 0.3*VDD 1.0 1.0
Unit
V V A A V
STH1(STH2), IOH=0mA STH1(STH2), IOL=0mA
VDD - 0.1 0.1 0.2 AVDD - 0.2 20 TBD 0.8 5 TBD 1.2 10
V V mV
Note 1 Note 2 Note 3 STH1 (STH2)
mA pF
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Logic Input Capacitance
.com excluded, TA=+25C
STH1 (STH2), TA=+25C
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CL2 Logic Input Capacitance Wiring Resistance AVDD Wiring Resistance AVSS Wiring Resistance VDD Wiring Resistance VDD CL2 RAVDD RAVSS RVDD RVSS
8 TBD 6 5 20 15
10 TBD
pF pF
TIVE JEC OB
Note 4 Note 4 Note 4 Note 4
Note 1: Deviation between input voltage and output value. Voltage on the output pin 30us after the rinsing edge of INH. VVIDEO= 0.2V to AVDD-0.2V. Note 2: FCPH=10MHz, X1 Simultaneous Clock Mode, TINH=63s, TIWL = 5us, No load. Note 3: Video input = AVDD/2, No Load. Note 4: Power and control signal are connected between each edge of the chips.
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AC Characteristics (TA= -30 to +75C, VDD= 2.7V to 5.25V, VSS=AVSS=0V, TR = TF = 5.0ns) Parameter
Clock Period
EK7601
Symbol
TCP
Condition
x1 Mode x3 Mode x1 Mode
MIN.
100 40 40 15 40 15 15 10
TYP.
MAX.
Unit
ns ns ns ns ns ns
Clock high-level width
TCWH x3 Mode x1 Mode
Clock low-level width
TCWL x3 Mode
Delay time Between Clocks STH Setup Time STH Hold Time RESET Pulse Width
TC12, TC23 TSS TSH TWR
x1 Sequential Mode
1/2*TCP
ns ns ns ns ns s ns ns
TIVE JEC OB
10 100 100 30 100 TDB
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RESET- INH Timing INH high-level width INH low-level width INH -STH Timing STH Pulse Delay Time Driver Output Delay Time
TRST-INH .com TIWH TIWL TINH-STH TSD TDD CL =20pF CL =25pF, RL=25k
DataShee
20 12 20
ns s
Load condition: Start pulse delay Time TSD on STH1 (STH2) output pin:
STH1(STH2) Output
20pF
Load condition: Driver Output Delay Time TDD on output buffers:
QA1 to QC80
25 k
Test point 25pF
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9. AC CHARATERISTICS WAVEFORM
EK7601
Unless otherwise specified, the input level is defined to VIH = 0.7 VDD, VIL = 0.3 VDD
x1 Mode
TCWH TCWL
79
TCP
80 81
TR
TF
CPH1 CPH2 CPH3
1
2
TC12
1 2 79 80 81
TC23
2
1
79
80
81
TSS TSH
TSS
STH input STH Output
TSD
TSD
x3 Mode
TCWH TCWL TCP TR TF
CPH1
t4U.com
STH input CPH1'
1
2
3
4
TSS TSH TSS
.com
5
234 235 236 237 238 239 240 241 242 243 244 245 243 244
DataShee
1
2
78
79
80
81
TSD
TSD
STH Output
RESET
TWR TRST-INH
STH input INH
TIWL
TINH-STH
TIWH
QA1 to QC80
Target voltage + 20mV
High-Z
TDD
Table 9.1:
AC characteristics waveform - 20 -
ON C
EN ID F
L IA T
Rev 1.0 Feb.21.2002
.com
DataSheet 4 U .com
www..com
EUREKA
10. RECOMMANDED SOLDERING CONDITIONS
EK7601
The following conditions must be met for soldering conditions of the EK7601. Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. EK7601: COF (TAB Package) Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C: heating for 2 to 3 Seconds: pressure 100g(per solder) ACF (Anisotropic Conductive Film) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm : time 3 to 5 seconds. Real bonding 165 to 180C: pressure 25 to 45 Kg/cm : time 30 to 40 seconds.
2 2
11. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and .com agree to fully indemnify Eureka for any damages resulting from such improper use or sale.
t4U.com
- 21 -
ON C
EN ID F
L IA T
Rev 1.0 Feb.21.2002
.com
DataSheet 4 U .com

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